1. Field of the Invention
This invention relates to use of embedded SRAM macro's in computer chips, and particularly to the use where the full chip function is maintained despite the loss of one or more embedded S RAM macro's.
2. Description of Background
SRAM (Static Random Access Memory) is commonly embedded in VLSI chips with other computing elements as an alternative to off-chip or stand alone SRAM. SRAM is added to a computer chip as a number of preconfigured SRAM instances. An instance of SRAM is also referred to as an SRAM macro. Each SRAM macro is a collection of static memory elements arranged in rows and columns, and also the associated control circuitry that provides the means to read and write addressable subsets of those memory elements. An SRAM macro typically includes some amount of redundant memory elements that may be used to replace defective memory elements.
Before our invention computer chips that used embedded SRAM's were subject to yield loss and field failures due to defects within the SRAM macros. The manufacturers added redundancy to the SRAM macros in the form of spare bit rows and columns to increase manufacturing yield and as result there was a reduction of the number of field replacements by allowing repair actions that circumvent defects. This approach works well, but its effectiveness diminishes as the percentage of area devoted to embedded SRAM increases. With increasing numbers of macros on a single chip, the likelihood of a single macro depleting all of its built in redundancy increases. This is due in part simply to the increased probability of a random set of defects or fails affecting a single macro, but also due to certain types of fails or defects which may be local in nature and consequently may adversely affect multiple elements of a single macro. Without another layer of redundancy, the loss of a single SRAM macro renders an entire chip unusable or degraded. In the level 2 cache chip for the IBM Z6 (Z6 is a code name for a planned chip for a core processor) computer system, the logical cache will have 768 separate SRAM macros which together account for 201 mm2 of the total chip area of 445 mm2. Pre-production defect and failure rate analysis has shown that redundancy within the SRAM macros alone is not sufficient to produce an acceptable manufacturing yield for this level 2 cache chip.